Interrupts

from sections 2.2 and 8.2.7 in the User's Guide

The interrupt priorities are fixed and defined by the arrangement of the modules inside the MSP430 chip. The nearer a module is to the CPU, the higher the priority. Interrupt priorities determine which interrupt is taken when more than one interrupt is pending simultaneously.

There are three types of interrupts:

  1. System Reset
  2. Non-Maskable Interrupts (NMI)
  3. Maskable Interrupts

Non-maskable interrupts are for hardware operation errors so there is no need to worry about these.

Maskable Interrupts

Maskable interrupts are caused by peripherals with interrupt capability including the watchdog timer overflow in interval-timer mode. Each maskable interrupt source can be disabled individually by an interrupt enable bit, or all maskable interrupts can be disabled by the general interrupt enable (GIE) bit in the status register (SR).

Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual.

Each pin in ports P1 and P2 have interrupt capability, configured with the PxIFG, PxIE, and PxIES registers. All P1 pins source a single interrupt vector, and all P2 pins source a different single interrupt vector. The PxIFG register can be tested to determine the source of a P1 or P2 interrupt.

Interrupt Flag Registers P1IFG, P2IFG

memory addresses 0x23 for P1, 0x2B for P2

Each PxIFG.x bit is the interrupt flag for its corresponding I/O pin and is set when the selected input signal edge occurs at the pin. All PxIFG.x interrupt flags request an interrupt when their corresponding PxIE bit and the GIE bit are set. Each PxIFG flag must be reset with software. Software can also set each PxIFG flag, providing a way to generate a software initiated interrupt.

if (P1IFG & BIT3) { // check if interrupt pending for P1.3

This bitwise AND operation will result in zero if P1.3 is not set, or a non-zero value (specifically the number 8) if P1.3 is set.

P1IFG &= ~BIT3; // clear pending interrupt for P1.3

This bitwise AND and NOT operation will clear the third bit in P1IFG. It will leave the rest of the bits in the register alone, so other potential pending interrupts are not cleared.

Only transitions, not static levels, cause interrupts. If any PxIFG.x flag becomes set during a port 1 or 2 interrupt service routine, or is set after the RETI instruction of a port 1 or 2 interrupt service routine is executed, the set PxIFG.x flag generates another interrupt. This ensures that each transition is acknowledged.

Interrupt Edge Select Registers P1IES, P2IES

memory addresses 0x24 for P1, 0x2C for P2

Each PxIES bit selects the interrupt edge for the corresponding I/O pin.

PIES |= BIT3; // select high-to-low transition for P1.3

This bitwise OR operation will set bit 3 in the P1IES register, leaving the other pins at whatever value they are set to before the statement is executed. Now the corresponding interrupt flag is set when the signal on P1.3 transitions from 1 to 0.

Interrupt Enable P1IE, P2IE

memory addresses 0x25 for P1, 0x2D for P2

Each PxIE bit enables the associated PxIFG interrupt flag.

P1IE |= BIT3; // enable the P1.3 pin to cause an interrupt

This bitwise OR operation will set bit 3 in the P1IE register, leaving the other pins at whatever value they are set to before the statement is executed. Now the corresponding flag in P1IFG will be set, provided global interrupts are also enabled.